Photonic circuits that survive the fab.
Waveguides, couplers, splitters and resonators designed with full-vector eigenmode analysis and verified with 3-D FDTD — including the fabrication-variation sensitivity that decides whether your layout works on the wafer, not just in the simulator.
The simulator always says yes
A nominal waveguide design is easy; a photonic circuit that hits spec across a real process window is engineering. Most PIC problems trace back to the same gaps: components designed in isolation that don't budget for fab variation, fiber-to-chip coupling treated as an afterthought, and free-space interfaces nobody owned. We design at the component and circuit level with the same tolerance-first discipline we apply to lens systems.
- Mode-engineered waveguides — geometry, bends and transitions with bend-loss and crosstalk budgets
- Couplers & splitters that hold spec — directional, MMI and adiabatic designs with corner analysis
- Fiber-to-chip coupling owned end to end — grating and edge couplers, plus the lensed free-space path when you need it
- Fab-variation sensitivity included — width / thickness / etch corners, not just nominal curves
What we design and simulate
Passive integrated photonics, delivered as foundry-ready geometry with simulation evidence.
Waveguides & Routing
Single-mode strip and rib geometries, bend radii and loss budgets, mode transitions and tapers, crosstalk-safe routing rules for dense layouts.
Couplers & Splitters
Directional couplers, MMIs and adiabatic splitters designed to target ratios — with wavelength dependence and process-corner behavior quantified.
Resonators & Filters
Ring and racetrack resonators: FSR, Q and coupling-regime design, thermal sensitivity estimates, and filter response synthesis.
Grating & Edge Couplers
Fiber-to-chip coupling designed for your fiber and packaging approach — coupling efficiency, bandwidth, and alignment-tolerance curves.
Free-Space-to-PIC Interfaces
Where photonic chips meet lenses — collimators, isolator trains, micro-optic relays — designed by a team that does both sides of the interface.
Variation & Yield Analysis
Corner analysis over width, thickness and etch depth; sensitivity ranking; design centering so performance holds across the process window.
Simulation you can take to a foundry
Component design starts with full-vector eigenmode analysis — effective indices, mode profiles, coupling coefficients — and is verified with 3-D FDTD before anything is frozen. Deliverables are engineering documents, not screenshots: geometry specifications against your foundry's layer stack, simulated S-parameters and spectra, sensitivity analysis, and a written design rationale your team can maintain.
- Eigenmode analysis — dispersion, birefringence, bend loss, coupling lengths
- 3-D FDTD verification — transmission, reflection and radiation where mode theory isn't enough
- Foundry-aware geometry — designed to your PDK layers and minimum features
- Documented rationale — why this geometry, what it's sensitive to, how to test it
Applications we support
- Datacom & interconnect — splitters, WDM building blocks, coupling structures
- Sensing — resonator-based and interferometric photonic sensors
- LiDAR & beam delivery — on-chip distribution feeding free-space emission optics
- Quantum & research photonics — low-loss routing and precision couplers for lab-to-chip programs
- Hybrid systems — where a PIC, a fiber and a lens assembly must work as one optical system
Silicon photonics questions
Which platforms do you design for?
Silicon-on-insulator (including standard 220 nm SOI), silicon nitride for low-loss and visible/NIR work, and other dielectric platforms. We design against your foundry's layer stack and design rules — tell us the PDK and we'll confirm fit.
Do you deliver GDS layouts?
Our core deliverable is verified component geometry and circuit-level design with simulation evidence — dimensions, spectra, S-parameters and sensitivity analysis your layout team can drop into the PDK flow. Component-level layout support is available as part of a design package; full-chip tape-out is handled with your layout team or foundry partner.
Can you fix a PIC that measured worse than simulation?
Often, yes — the same root-cause discipline we apply to lens audits works on chips. Typical culprits: un-budgeted fab variation, coupler wavelength sensitivity, thermal drift and fiber-coupling losses attributed to the wrong component. We re-simulate against measured geometry and give you a ranked correction path.
We also have lenses and fibers in the system — can you own the whole path?
That's exactly our sweet spot. Because we design imaging and laser optics as well as waveguides, we can own the full photon path — chip, coupler, fiber, micro-optics and free-space train — as one budgeted optical system instead of three vendors' boundary problems.
Building a photonic chip or a hybrid photonic system?
Start with a fixed-scope feasibility study: component architecture, first-order performance, process-window risk — decision-ready before you commit to a tape-out.